1. Field of the Invention
This invention relates to a memory circuit, and more particularly to a memory circuit having a decoder of small power consumption.
2. Description of the Prior Art
Generally, one-bit data are written into and read from memory circuit in the following manner. First, n-bit binary address signals are supplied to a decoding circuit. Then a decoding circuit decodes the n-bit binary signals, thus enabling only that word line out of 2.sup.n word lines which have been address-designated. Through the enabled word line one-bit data are supplied to or from the memory cell of the memory circuit.
Such a known memory circuit is shown in FIG. 1. Binary address signals A.sub.0, A.sub.1, . . . A.sub.n-1 are supplied to address buffers 1. The address buffers 1 generate signals A.sub.i (i=0, 1, . . . n-1) and signals A.sub.i (i=0, 1, . . . n-1) obtained by inverting the signals A.sub.i. The signals A.sub.i and the signals A.sub.i are supplied to decoder 2. The decoder 2 has output lines W.sub.j (j=0, 1, . . . 2.sup.n -1) which are connected respectively to rows of memory cells constituting a memory cell array 3. Thus an output signal of the decoder 2 designates the cells of one row.
The decoder 2 comprises a plurality of decoding circuits 20 to which the output lines W.sub.j are connected, respectively. Each decoding circuit 20 is supplied with signals at point 201 (indicated by black dots in the drawing). When all the binary address signals A.sub.i have a logic value "0" and thus designate a 0th address, the word line W.sub.0 of the decoder circuit 2 is enabled. In this case the decoder unit 20 functions as a NOR circuit.
The memory circuit further comprises a chip selection terminal CS. The terminal CS is connected to a CS buffer IC, whose inverted output signal CS is supplied to all the decoding circuits 20 of the decoder 2. Thus, when a chip selection signal CS supplied to the chip selection terminal CS, all the word lines W.sub.j are disabled and all the decoding circuits 20 are also disabled. As a result, no data can be written into or read from the memory cell array 3.
Each decoding circuit 20 of the known decoder 2 is shown in FIG. 2. As shown in FIG. 2, the decoding circuit 20 comprises MOS transistors. It functions as a NOR circuit and supplies an output of a logic value "1" through its word line WD only when a chip selection signal CS has a logic value "1" and, at the same time, all the address signals A.sub.0, A.sub.1, . . . A.sub.n-1 have a logic value "0". More specifically, when transistors Q.sub.0 -Q.sub.n-1 are off and a transistor T.sub.1 is on, a transistor T.sub.2 is turned on because its gate terminal receives a power source voltage V.sub.CC through a load MOS transistor T.sub.3. Since the gate terminal of a transistor T.sub.4 receives a low-level output from an inverting transistor T.sub.5 which receives a high-level input signal and since the transistor T.sub.2 is on, a chip selection signal CS of a logic level "1" appears in the word line WD. It follows that the decoding circuit 20 is selected and that the 0th address is designated.
Conversely, when at least one of the address signals A.sub.0 -A.sub.n-1 has a logic value "1", the transistor Q.sub.0, Q.sub.1, . . . or Q.sub.n-1 which receives the address signal is turned on. As a result, the transistor T.sub.5 is turned off and the transistor T.sub.4 is turned on. Consequently current flows along a route constituted by the transistor T.sub.3, the transistor T.sub.1 and the transistor Q.sub.i (i=0, 1, . . . or n-1) which is on. A chip selection signal CS of a logic value "0" therefore appears in the word line WD.
In the above-mentioned decoding circuit 20 current inevitably flows along the route consisting of T.sub.3, T.sub.1 and at least one transistor Q.sub.i (i=0, 1, . . . or n-1).
In the known decoder 2, N-1 word lines out of N word lines corresponding to the total number N of memory words (N=2.sup.n) are not selected and are kept at logic "0". Obviously there must flow within the decoder 2 an electric current which keeps the non-selected word lines at logic value "0". Hence the decoding circuit 20 consumes much power. In the existing static RAM, for instance, such a decoder uses up about 35% of the power that the whole RAM consumes.